The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
Accordingly, the semiconductor dies need to have increasingly greater numbers of I/O pads packed into smaller areas, and the density of the I/O pads rises quickly. As a result, the packaging of the semiconductor dies becomes more difficult, which adversely affects the yield of the packaging. Post-passivation interconnect (PPI) structures have been used to route the connections from the semiconductor dies, increase numbers of I/O pads, redistribute the bump layout, and/or facilitate contact to the package.
Existing PPI structures can suffer from shortcomings in circuit routing. For example, existing PPI structures have less flexible circuit routing capabilities. As a result, more PPI layers may be needed to provide more routing area to overcome signal integrity issues, which may need a smaller process window and incurs higher cost.